Solid-state Fault Current Limiter Research Articles

Experimental analysis of a multi-phase resonance-based fault current limiter prototype under symmetrical and asymmetrical faults

Expansion of power systems and involving more distributed generation cause to increase in fault current levels. This paper presents a three-phase resonance-based solid-state fault current limiter (FCL) prototype that has series and parallel resonance modes developed to suppress fault currents of power systems. The laboratory-scaled prototype is located on a three-phase test circuit and has been examined with the fault types of three-phase, three phase-to-ground, two phase-to-ground, and phase-to-ground. The performance and effectiveness of the proposed series-parallel resonance-type fault current limiter (SPRFCL) are validated with the comparison of Matlab/Simulink simulations and experimental test results. Fault currents in different types of faults are limited to an allowable value at high rates and experimental results are considerably close to current values obtained from each fault simulation. Fault currents of faulted phases are restricted with the limiting rates ranging from 75 % to 85 % concerning prospective fault currents in the non-FCL situations. Short-circuit test results of the prototype of SPRFCL that is supplied from a 380 V grid revealed that it acts stable and successful operation regardless of fault type. Accordingly, it has a favorable circuit design for power system applications.

Multi-physics modelling and performance analysis of an air-core reactor in the framework of solid-state fault current limiters

This study presents a comprehensive multi-physics modelling of an air-core reactor operating within a solid-state fault current limiter. By utilizing an air-core reactor in the solid-state fault current limiter, it is aimed to avoid magnetic saturation and assess a conventional fault current limiting device within a contemporary fault current limiter topology. Within the employed fault current limiter topology, the air-core reactor not only limits fault current during grid faults but also carries nearly the entire network current under normal operational conditions. Therefore, the performance of air-core reactor is investigated through thermal, electromagnetic and electrostatic aspects for normal and fault conditions. A 380 V test prototype is employed to validate the coupling of reactor model and electric circuit dynamics in the simulations. Furthermore, current results of high voltage simulations are supported by PSCAD results to reveal the results accuracy. During the operation of air-core reactor in normal and fault cases, the distribution of heat originating from eddy and resistive losses was examined through convection, radiation and conduction mechanisms. Moreover, the electric field intensities affecting the reactor are obtained for different operating conditions through electrostatic analysis, whereas the electromagnetic analysis reveals the magnetic flux densities and magnetic forces acting on the reactor.

Efficient practical method for differential protection of power transformer in the presence of the fault current limiters

AbstractThe algorithms of the present generation of practical differential relays are based on two methods. The first method is based on the ratio of the harmonic content of the differential current, and the second one is based on the length of the time interval between the zero‐crossing points of the differential current, called the gap‐detection method. However, these methods suffer from the installation of the fault current limiters (FCLs) in the power system and current transformer (CT) saturation phenomenon. This paper deals with a simple practical method for differential relays to secure their performance. In the suggested method, a classifying algorithm is used to categorize the input signal of the relay and then the best method of the present generation of differential relays is employed. By this simple decision, the method takes the advantage of harmonic‐based and gap‐detection methods, while avoiding their drawbacks. To prove the robustness of the suggested method, a test bench with a resistive solid‐state fault current limiter (SSFCL) is implemented and examined in different situations. The results validate the consistency and the accuracy of the modified technique not only in the absence and the presence of the FCL but in the case of CT saturation.

Analysis and experimental tests of a solid-state fault current limiter

Analysis and experimental tests of a solid-state fault current limiter

Reduction of the DC Circuit Breaker Requirements by Bidirectional Solid-State Fault Current Limiter in DC Grid

Reliable and economic protection of DC grids against fault currents is the main challenge for the development of voltage source converter-based DC grids. Application of fault current limiters (FCLs) can limit the rapid increase of fault current and reduce the DC circuit breaker (DCCB) requirements to isolate the fault. This article reports a bidirectional solid-state FCL (BSSFCL) to protect the DC lines against DC short circuit fault. In addition, it can limit fault current in both directions. The circuit and principle operating of the proposed BSSFCL are presented. Then, the current limiting performance of the proposed BSSFCL is analyzed and its parameter design requirements are presented. Finally, the performance of the proposed BSFFCL is compared with that of the RL-current limiting circuit (RL-CLC), mutual inductance-type FCL (MIFCL), and restive mutual-inductance solid-state FCL (RMI-SSFCL). The numerical analysis and simulations were done using the PSCAD/EMTDC software. It was found that, the BSSFCL could effectively enhance the breaking capability of DCCBs. Moreover, it outperforms the RL-CLC, MIFCL, RMI-SSFCL in terms of the fault current limiting, the fault clearing time and metal oxide arrester (MOA) energy absorption of DCCBs.

Low-Voltage Ride Through Enhancement of Both DFIG and SEIG-Based Wind Power Plants by RC-Type Solid-State Fault Current Limiter

The low-voltage ride-through (LVRT) is the main requirement of grid codes for integration of wind power plants (WPPs) to the power system. This paper proposes a RC-type solid state fault current limiter (SSFCL) to enhance the LVRT requirement of WPPs. It is based on the RL-type SSFCL in which its configuration is changed to satisfy the LVRT requirements. To evaluate the proposed RC-type SSFCL performance, extended time domain simulations are executed in PSCAD/EMTDC software environment. Also, the performance of the RC-type and RL-type SSFCLs are compared under both symmetrical and asymmetrical fault conditions to show the efficiency of the proposed RC-type SSFCL. Both doubly-fed induction generator (DFIG) and self-excited induction generator (SEIG) are used to examine the RC-type SSFCL performance. Based on simulation results, the RC-type SSFCL provides an effective hardware scheme to augment the LVRT requirements of both DFIG and SEIG based WPPs and outperforms the RL-type SSFCL.

Design of Self-Powered Solid-State Fault Current Limiters for VSC DC Grids

Abstract-Fault current limiters (FCLs) can suppress the rise of short-circuit fault currents in voltage source converter (VSC) based DC grids. However, the power electronic switches of FCLs need extra source equipment to supply the required power, which increases complexity and cost. This paper presents three kinds of self-powered solid-state FCLs (SSFCLs). The proposed self-powered SSFCLs detect short-circuit faults by sensing fault current increases and draw energy from the fault DC line to automatically drive the power electronic switches. The self-powered SSFCLs are equipped with a self-powered supply system (SPSS). The SPSS obtains energy from the magnetic field induced by short-circuit fault current using magnetic-coupling mutual inductance coils. In PSCAD/EMTDC, the proposed self-powered SSFCLs are placed directly on the DC line without external power supply equipment. When a short-circuit fault occurs, the simulation results verify that the proposed self-powered SSFCLs can rapidly acquire power to drive the power electronic switches and then suppress the rise of the fault current. The proposed self-powered SSFCL prototypes provide a solution for decreasing the cost and complexity associated with installing extra source equipment.

A modified bridge-type nonsuperconducting fault current limiter for distribution network application

The electrical distribution network is undergoing tremendous modifications with the introduction of distributed generation technologies which have led to an increase in fault current levels in the distribution network. Fault current limiters have been developed as a promising technology to limit fault current levels in power systems. Though, quite a number of fault current limiters have been developed; the most common are the superconducting fault current limiters, solid-state fault current limiters, and saturated core fault current limiters. These fault current limiters present potential fault current limiting solutions in power systems. Nevertheless, they encounter various challenges hindering their deployment and commercialization. This research aimed at designing a bridge-type nonsuperconducting fault current limiter with a novel topology for distribution network applications. The proposed bridge-type nonsuperconducting fault current limiter was designed and simulated using PSCAD/EMTDC. Simulation results showed the effectiveness of the proposed design in fault current limiting, voltage sag compensation during fault conditions, and its ability not to affect the load voltage and current during normal conditions as well as in suppressing the source powers during fault conditions. Simulation results also showed very minimal power loss by the fault current limiter during normal conditions.

Modified Solid-State Fault Current Limiter based on AC/DC Reactor

This study presents a modified solid-state fault current limiter (SSFCL) based on AC/DC reactor, which limits both transient and steady-state fault currents under fault condition. It includes two diodes and one Insulated-gate bipolar transistor (IGBT) switch. The number of semiconductor switches in the proposed AC/DC reactor SSFCL is a quarter and half of the semiconductor switches employed in the fully-controlled and conventional AC/DC reactor BFCL, respectively. It offers lower cost, simple structure and more reliability comparing with the conventional models. Also, the inductance and current rating of AC/DC reactor used in the proposed AC/DC reactor SSFCL is equal to the fully-controlled and conventional AC/DC reactor BFCL. The power circuit and principle operation of the modified AC/DC reactor SSFCL are presented. Then, the analysis of normal and fault operating conditions of the proposed AC/DC reactor SSFCL are provided. Finally, the performance of the proposed AC/DC SSFCL is verified by both PSCAD/EMTDC simulation and experimental results.

Certain investigations on fault analysis in a smart grid system using S-transform and their fault ride through using solid-state fault current limiter

This paper investigates certain fault analysis such as fault detection, identification and classification and their fault ride through (FRT) technique in a smart grid (SG) system using Stockwell transform (ST) and solid-state fault current limiter (SSFCL). ST when applied to symmetrical and asymmetrical faults for the detection and identification in a SG System yields a ST amplitude matrix (STA). The nature of the fault is identified through the features extracted from ST. STA with probabilistic neural network (PNN) classifier helps to detect the types of fault through the features extracted from fault signal. The outcome of PNN helps to classify the nature of fault like single-phase, two-phase and three-phase faults individually and with respect to ground fault in a SG system. Also, limiting the fault current ensures the continuous operation and reliability of SG under fault conditions. Further to avoid the disconnection of wind turbine system and solar PV system from the grid and overcome block out issue, SSFCL is employed. It improves the FRT capability of a SG system by controlling the fault current within the specified limit and retains the wind turbine system and solar PV system connected with the grid. The suggested scheme is modeled and the results are verified through the time domain simulation using MATLAB.

Plug-in gate-loop compensators for series-connected IGBT drivers in solid-state fault current limiter

Solid-state fault current limiter (SSFCL) is the key protective equipment in direct current distribution network. To meet the high voltage requirement meanwhile reduce the cost, implementing a SSFCL based on series-connected insulated gate bipolar transistors (IGBTs) is a promising way. However, voltage unbalancing of IGBTs would be introduced if the gate-loops of the IGBTs are non-identical. In this paper, a plug-in gate-loop compensator with discrete gate voltage feedback and pulsewidth current compensation is proposed. The main merits are 1) with the plug-in structure, the extra current sources only provide small power to fine-tune the gate-loop without affecting the functions provided by the commercial IGBT gate driver; 2) the gate-emitter voltages of IGBTs are compared with the preset thresholds to obtain control criterions, and the pulsewidths of the current sources are controlled for gate-loop compensation, thus both analog-digital and digital-analog converters are avoided; 3) the control law is easy to be implemented in FPGA, and is robust to voltage variation of power-loop. With the proposed compensator, the voltage unbalancing is alleviated immediately at the present switching cycle, and further eliminated cycle-by-cycle during current limitation process. Experimental results verify the feasibility of proposed compensator.

Solid-State Fault Current Limiters for Residential Houses and Commercial Buildings

This paper presents an overview and techno-economic feasibility study of solid-state fault current limiters (SSFCL) for low-voltage residential and commercial applications. An SSFCL is proposed to be installed upstream inside a conventional panelboard or load center. The simulation results demonstrate the effectiveness of utilizing SSFCL for residential houses and commercial buildings and the advantages of fast fault current limiting and great reduction of fault energy. Some physical design considerations are made for installing an SSFCL including their fault-current-limiting inductors inside a panelboard or load center. The proposed SSFCL solution potentially has best overall benefits compared to the conventional mechanical solution and other solid-state-based solutions.

Optimal placement of dynamic voltage restorer – solid state fault current limiter combination for global voltage sag mitigation in distribution system

Abstract - One of popular and effective solutions to voltage sag mitigation is the use of custom power devices (CPD) like dynamic voltage restorers (DVR). On the other hand, fault current limiter FCL) also has impacts on voltage sags caused by faults. This paper introduces a new combination between DVR and solid-state fault current limiter (SSFCL) that can further improve global performance of voltage sags due to faults in distribution system. The location of DVR-SSFCL combination is optimally selected basing on minimizing a global index - SARFIX. In optimizing DVR-SSFCL combination’s placement, various cases of parameters relating with its ratings are considered and discussed. The paper uses IEEE’s 33-bus distribution system for modeling voltage sag due to faults and DVR-SSFCL combination’s effectiveness on global voltage sag mitigation.

A DC-Reactor-Based Solid-State Fault Current Limiter for HVdc Applications

Expansion of high-voltage dc (HVdc) systems to multi-terminal HVdc (MT-HVdc) systems/grids considerably increases the short-circuit levels. In order to protect the emerging MT-HVdc systems/grids against fault currents, proper dc fault current limiters (FCLs) must be developed. This paper proposes an innovative high inductance solid-state dc-reactor-based FCL (HISS-DCRFCL) to be used in HVdc applications. In fact, during the HISS-DCRFCL normal operation, its inductance value is extremely low, and its value becomes considerably high during the fault period, which decreases the fault current amplitude. The proposed HISS-DCRFCL performance is analyzed by MATLAB/Simulink and the simulation results are verified and confirmed by laboratory experimental results using a scaled-down laboratory prototype setup.

Influence of Solid State Fault Current Limiter on Grid Connected Photovoltaic System Protection

Influence of Solid State Fault Current Limiter on Grid Connected Photovoltaic System Protection

Low voltage ride-through capability improvement methods for DFIG based wind farm

In this paper the low voltage ride-through (LVRT) capability enhancement of the DFIG based wind farm (WF) is accomplished by using of the existing series devices like the new bridge type fault current limiter (NBFCL), new solid-state fault current limiter (N-SSFCL), resistive solid-state fault current limiter (R-type SSFCL), inductive-resistive type solid-state fault current limiter (SSFCL-LR), and series dynamic braking resistor (SDBR). The LVRT analysis is done among the series devices in terms of LVRT capability improvement performances, implementation feasibility, and cost. A temporary balanced and unbalanced fault was applied in the DFIG based 15MW test model system to demonstrate the LVRT performance among the series devices. In this work, all simulations were executed in Matlab/Simulink software and from all simulation results, it can be stated that the mentioned all series devices can augment the LVRT capability during the fault, however the performance of the NBFCL and the N-SSFCL are most impressive in comparison to others.

Design and Implementation of Fault Current Limiters in Distribution System Using Internet of Things

One of the essential execution of a wireless sensor network is observing hardware. Wireless Sensor Network are capable for taken a toll effective checking over gigantic geo location. Development of keen network depends on the Internet of Things (IoT). Nowadays the fault current levels are increased because of the increasing power demand. Fault Current Limiter(FCL) is used as a protective device to reduce the fault current in distribution system. This paper presents Solid State Fault Current Limiter (SSFCL) and Hybrid Fault Current Limiter (HFCL) to limit the fault current levels for different fault conditions. Also this paper presents the comparison between these two devices with fault current limiting ratio. The performance of the two devices is carried over in IEEE 6-bus system. The simulation and experimental results validate the performance of these two devices to reduce the fault current. The proposed model is executed with SSFCL and HFCL for 60 W three-phase load under various fault conditions. All the fault conditions are observed and controlled through IoT cloud framework.

Solid State Fault Current Limiter (SSFCL) in Power System – A Case Study

Increasing generation to meet the load growth and interconnections between systems to improve reliability and power transfer capability are likely to increase the fault current levels. If the resultant short circuit current exceeds the existing equipment rating, they must either be upgraded or replaced or reconfigure its system to reduce the new available fault current. Both of which are very costly or time escalated process. Hence it is preferred to explore the feasibility of utilization of existing equipment with current limiting devices. Current limiting using passive element like series inductor reduces system stability and load flow. To overcome this problem, the series reactor is made to come into services only for the duration of fault. This paper proposes new methods for fast acting current limiting using Solid State Fault Current Limiters (SSFCL) that employs power electronic switches to overcome the limitation of the passive current limiters. Modeling and simulations of these methods are performed on a typical 400 kV power system using PSCAD/EMTDC. The results of which confirm that the fault level can be effectively reduced.

Improvement of Transient Stability of Dfig Based Wind Generator by Resistive Type Solid State Fault Current Limiter Using Fuzzy Controller

Improvement of Transient Stability of Dfig Based Wind Generator by Resistive Type Solid State Fault Current Limiter Using Fuzzy Controller

Reliability analysis of component-level redundant topologies for solid-state fault current limiter

ABSTRACTExperience shows that semiconductor switches in power electronics systems are the most vulnerable components. One of the most common ways to solve this reliability challenge is component-level redundant design. There are four possible configurations for the redundant design in component level. This article presents a comparative reliability analysis between different component-level redundant designs for solid-state fault current limiter. The aim of the proposed analysis is to determine the more reliable component-level redundant configuration. The mean time to failure (MTTF) is used as the reliability parameter. Considering both fault types (open circuit and short circuit), the MTTFs of different configurations are calculated. It is demonstrated that more reliable configuration depends on the junction temperature of the semiconductor switches in the steady state. That junction temperature is a function of (i) ambient temperature, (ii) power loss of the semiconductor switch and (iii) thermal resistance of heat sink. Also, results’ sensitivity to each parameter is investigated. The results show that in different conditions, various configurations have higher reliability. The experimental results are presented to clarify the theory and feasibility of the proposed approaches. At last, levelised costs of different configurations are analysed for a fair comparison.